(1) Field of the Invention
The present invention relates to a process in which metal oxide semiconductor field effect transistor, (MOSFET), devices are fabricated, and more specifically to a process used to fabricate MOSFET devices with very narrow channel lengths.
(2) Description of Prior Art
The semiconductor industry is continually trying to decrease the cost of semiconductor chips, specifically chips comprised with MOSFET devices, while always striving to improve the performance of the semiconductor chip, or the performance of an individual MOSFET device. These objectives have been in part realized via the ability of the semiconductor industry to utilize submicron features, micro-miniaturization, in semiconductor chips. The ability to achieve micro-miniaturization has been realized via advances in specific semiconductor fabrication disciplines, mainly photolithograhy and anisotropic dry etching. For example the use of more sophisticated exposure cameras, as well as the development of more sensitive photoresist materials, has resulted in the routine attainment of submicron images in photoresist layers. In turn the development of reactive ion etching, (RIE), tools and processes, has allowed the submicron images in photoresist layers to be easily transferred to underlying materials used in the fabrication of semiconductor devices. However to continue to improve the performance of MOSFET devices, specifically areas of the MOSFET device have to be properly engineered to optimize performance.
MOSFET devices with channel lengths less then 0.35 uM, or deep submicron MOSFET devices, are now being fabricated, resulting in improved device performance. The smaller features of the deep submicron MOSFET device results in a decrease in parasitic capacitances, which in turn results in a performance increase, when compared to MOSFET counterparts, fabricated with larger dimensions. However there still remains specific areas of the deep submicron MOSFET device, in which additional, undesired parasitic capacitance adversely influence performance. For example the threshold voltage adjust region, created in the channel region of the MOSFET device, results in a significant level of junction capacitance. This invention will describe a fabrication method for creating deep submicron MOSFET devices, in which the unwanted junction capacitance, resulting from a threshold voltage adjust region, is reduced. This is accomplished by restricting the width of threshold voltage adjust region to a width identical to the width of a narrow polysilicon gate structure. The ability to self align the narrow polysilicon gate structure to a local threshold voltage adjust region, is accomplished via a unique processing procedure, featuring an ion implantation step, in a hole opened in a dielectric layer, to create the local threshold adjust region. A polysilicon refill process, used to fill the hole in the dielectric layer, and a silicidation procedure, used to remove the unwanted polysilicon, are then performed, resulting in the creation of the narrow polysilicon gate structure, self aligned to the local threshold voltage adjust region. Prior art such as Hong, et al., in U.S. Pat. No. 5,489,543, uses a threshold voltage adjust region formed via ion implantation through a polysilicon layer, and a gate insulator layer, into the underlying semiconductor substrate. This invention will describe a polysilicon gate structure formed after creation of a local threshold voltage region, self aligned to the local threshold voltage adjust region via use of an opening in a dielectric layer, used for both the threshold voltage adjust, and the polysilicon gate structure definition.